Problem with ARM AT91SAM7S512 Flash bank

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Nico595
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Problem with ARM AT91SAM7S512 Flash bank

Postby Nico595 » Tue Mar 19, 2019 12:52 am

Hi,

I have a problem with ARM AT91SAM7S512. Yesterday my compiled file exceeds 0x0003FFFF. With this ARM, the flash bank is composed into 2 parts of 256KB.For my mapping, the start address is 0x0. The end of the first flash bank is 0x0003FFFF. But when my file needs the second flash bank, I lose the data.

I use UVision5 with JTAG ULink2 interface for upload the compiled file. No problem about the transfer, no error, just a small stop when the address is 0x00040000.

I checked the .ld file, the address of Flash bank is correct : 0x0 - 0x0007FFFF

Do you have an idea ?
Thank you very much for your help.

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Re: Problem with ARM AT91SAM7S512 Flash bank

Postby Nico595 » Tue Mar 19, 2019 7:33 pm

After investigation I think the setup of Uvision is good. I have the verify function and no problem are detected when the file is send in the flash bank 0 and the flash bank 1. The .hex file genered by GCC is correct, mapping and data.

I found this information :

Code: Select all

I found another solution to this problem. You can use the AT91SAM7S512 part, which has two independent banks 256K flash and two independent flash controllers. You can run your program from the first bank using the first flash controller while writing the second bank using the second flash controller. I initialized MEDFlash with EFC1 instead of EFC0:

FLA_Initialize(&(medias[numMedias]), AT91C_BASE_EFC1); // init flash controller 1 instead of 0

and then I changed the flash base address to 0x00140000 and flash memory size to 0x00040000 so I wouldn't overwrite my program memory.

media->baseAddress = (unsigned int) 0x00140000;
media->size = 0x00040000;

I am using the first bank of flash for program memory and the second for mass storage. It works great.


http://www.at91.com/viewtopic.php?t=4254


Thanks,

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Re: Problem with ARM AT91SAM7S512 Flash bank

Postby Nico595 » Tue Mar 19, 2019 10:45 pm

I found this code for init register bits of the flash bank0 and flash bank1 on AT91SAM7S512. But I have error on MC0_FMR and MC1_FMR when I compile in C with Flowcode.

Code: Select all

  /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/
#if SAM7_PLATFORM == SAM7X512
  AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
  AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
#else
  AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
#endif


https://github.com/matrix-io/matrix-cre ... /hal_lld.c

For information, I write the low level code. In the low level code, actually I only this line for init the flash bank.

Code: Select all

 AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;

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Re: Problem with ARM AT91SAM7S512 Flash bank

Postby Nico595 » Wed Mar 20, 2019 9:12 am

Fixed with add init bank0/1 code in the low level and the AT91SAM7S512.h declaration in the Def init sequence.

Code: Select all

AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
  AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;



:D :D :D