SPEED CAN-BUS inernal external

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LeighM
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Re: SPEED CAN-BUS inernal external

Postby LeighM » Fri Feb 08, 2019 3:06 pm

Looks like you are using software SPI, could you try a different Sample Point, e.g. Middle?
Also the "While Free1" loop should have the test the loop at "End"

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Re: SPEED CAN-BUS inernal external

Postby Barmaley_GMN » Fri Feb 08, 2019 8:15 pm

This variant sends only one message

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36,010 6C1      8 01 01 00 03 00 00 00 00 ASCII:


And it always compile hex with mistake in configuration chip. It sets bits 5 and 7 in address 30000 as 1. But they can't be set as 1.
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Re: SPEED CAN-BUS inernal external

Postby LeighM » Mon Feb 11, 2019 10:39 am

so you need to go back to the version that masks the status with 0x04, just to get the Tx Buffer 0 status
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Re: SPEED CAN-BUS inernal external

Postby Barmaley_GMN » Mon Feb 11, 2019 6:20 pm

Thanks!
It helps!

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FCR_RETVAL = FC_CAN_SPI_CAN_Status_2(160);
FCV_FREE1 = FCR_RETVAL & 0x04;

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Re: SPEED CAN-BUS inernal external

Postby Barmaley_GMN » Mon Feb 11, 2019 7:48 pm

Barmaley_GMN wrote:Thanks!
It helps!

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FCR_RETVAL = FC_CAN_SPI_CAN_Status_2(160);
FCV_FREE1 = FCR_RETVAL & 0x04;


How about configure bits?
____
I solve (attachment).

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 <format >
            <byte value='0x1F' />
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