Moment of IOC

[Jan Lichtenbelt]

At which level (which voltage) will there an Interrupt On Change on a falling edge and on a rising edge?

With kind regards

Jan Lichtenbelt

[EtsDriver]

After taking some readings, here's what I have found. The falling edge trip point was about 2.0V (it should be 1.0V, as per the docs). At that point, the IOC interrupt is tripped. Inside the int routine I clear (or try to clear) the interrupt flag IOCAF2. It doesn't clear! Or I should say, it WON'T clear until I drop the voltage down past 2.0V, THEN it will clear. Leaving the voltage set at the trip point causes the interrupt to recycle, causing more software counts to be accumulated.

From what I read in the specs, after tripping on the falling edge, the Schmitt trigger levels should change to prevent multiple trips around that trip point. This is not happening. Even at the TTL levels, it should not do what it's doing.

I can try to work around this by removing the falling edge interrupt and enabling the rising edge, which itself would then flop back to the initial mode (ie, a "manual" Schmitt trigger implementation). Seeing that I have 2 hours to get this done, I don't see any other solution.

Hardware or software problem?

Source

So conclusion after reading that thread, i think even microchip might not know exactly!

Another forum thread:

About input logic threshold level for pic 16F628