There is bug in the DsPIC internal CAN component, then component can never set the baudrate,rx mask or filters, because the reqop config mode value is wrong..
The REQOP bits are CiCTRL 10-8 and the config mode is 100, so when requestin config mode, the CiCTRL register value should be 0b10000000000 = 0x0400...
But the define value is 0x80.
I mean this:
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//CANCTRL
#define REQOP_CONFIG 0x80
#define REQOP_LISTEN 0x60
#define REQOP_LOOPBACK 0x40
#define REQOP_SLEEP 0x20
#define REQOP_NORMAL 0x00
But maybe better solution is write only the REQOP bits, in the CiCTRL register, that way entering or exit in the config mode don't write other bits in the CiCTRL register (like the CANCKS), which should be set if fcan is 30MHz or higher...
Here is the way what I mean:
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#define REQOP_CONFIG 0x04 //changed by mikat
//configure CAN I/O - ds30F??
// Request config mode.
C1CTRLbits.REQOP = REQOP_CONFIG; //changed by mikat
// Wait till desired mode is set.
while( C1CTRLbits.OPMODE != 0x04 ); //changed by mikat
// Now set the baud rate.
//Setup the CAN comms Masks and Filters
// Request normal mode.
C1CTRLbits.REQOP = REQOP_NORMAL; //changed by mikat
// Wait till desired mode is set.
while( C1CTRLbits.OPMODE != 0x00 ); //changed by mikat
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//configure CAN I/O - ds30F??
// Request config mode.
C1CTRL = REQOP_CONFIG;
// Wait till desired mode is set.
while( (C1CTRL & CAN_OP_MODE_BITS) != 0x80 );
// Now set the baud rate.
//Setup the CAN comms Masks and Filters
// Request normal mode.
C1CTRL = REQOP_NORMAL;
// Wait till desired mode is set.
while( (C1CTRL & CAN_OP_MODE_BITS) != 0x00 );
The Flowcode also gives warning at the unconnected chipselect pin, when the internal can is used..
The SPI component gives compiler error, if the DAC enable and NVM enable pins are unconnected, could there be not used option, that those don't "waste" i/o pins, when are unused?
The onewire component seems to have bug, which is included both, the 8 and 16 bit version, the scanbur or devicecount function don't work, so the code don't get the device rom address..
Btw. is there any plans at the internal can at the 33 and 24f devices?
I'll try to make code for those chips internal can, but then I hit the wall, the tx and rx buffers goes via DMA transfer, and that is too complicated to my skill...
Mika