Page 3 of 3
Re: SPEED CAN-BUS inernal external
Posted: Fri Feb 08, 2019 3:06 pm
by LeighM
Looks like you are using software SPI, could you try a different Sample Point, e.g. Middle?
Also the "While Free1" loop should have the test the loop at "End"
Re: SPEED CAN-BUS inernal external
Posted: Fri Feb 08, 2019 8:15 pm
by Barmaley_GMN
This variant sends only one message
Code: Select all
36,010 6C1 8 01 01 00 03 00 00 00 00 ASCII:
And it always compile hex with mistake in configuration chip. It sets bits 5 and 7 in address 30000 as 1. But they can't be set as 1.
Re: SPEED CAN-BUS inernal external
Posted: Mon Feb 11, 2019 10:39 am
by LeighM
so you need to go back to the version that masks the status with 0x04, just to get the Tx Buffer 0 status
Re: SPEED CAN-BUS inernal external
Posted: Mon Feb 11, 2019 6:20 pm
by Barmaley_GMN
Thanks!
It helps!
Code: Select all
FCR_RETVAL = FC_CAN_SPI_CAN_Status_2(160);
FCV_FREE1 = FCR_RETVAL & 0x04;
Re: SPEED CAN-BUS inernal external
Posted: Mon Feb 11, 2019 7:48 pm
by Barmaley_GMN
Barmaley_GMN wrote:Thanks!
It helps!
Code: Select all
FCR_RETVAL = FC_CAN_SPI_CAN_Status_2(160);
FCV_FREE1 = FCR_RETVAL & 0x04;
How about configure bits?
____
I solve (attachment).