Matrix user forums

Hi

I have a 18F46K22, using FC6 (6.1.2.0) that uses a device on spi bus

running the processor on 16mhz, with Fosc/4 (4mhz spi) setting for spi bus....i get correct
operation of the device(ADXL345 acc)...device_ID register correct (0xE5)

If i run the processor at 64mhz PLL....with Fosc/16 (also 4mhz spi)....i get a strange
reading back from the device_ID register (0xE4)....which indicates a dropped bit (lsb)
in that value when read out from the ID register...and other subsequent values from
other registers are not correct

Since spi bus is clocked at same speed (4mhz...in spec of chip which is max 5mhz)....i am
now stuck...dont know how to resolve this
I tried a delay after CS on the device but also no luck

Any ideas?

Hello,

Have you tried changing the clock polarity and phase as well as the sample point settings of the SPI component? Sometimes changing one or more of these settings will make the communications more reliable. Also make sure that the CS pin is disabled when you initialise the SPI to ensure the device isn't getting any spurious clock edges.

Hi Ben

So far as i remember, the clock phase etc works only with a certain setting
and the CS is always de-asserted on startup, its one of the first things that
is done, CS only toggled on macros for reading/writing.....

Maybe i should the PLL 64mhz on the FC7 version compiler i have as a process
of elimination?

Reason i want to run the processor at 64mhz is for some lengthy maths calcs
that i would like to speed up

Lets see what gives with the FC7 compiler?

Thanks

Mark