ADC stability problem

[howard123]

Hello, I am using a 18F4550 with 12 ADCs enabled from which I am getting unexpected results. They on occasion will be out by about 3% but are most often accurate. My source and Vref voltages are stable and are as defined in the datasheet.
I have a question around the ADC successive approximation period [TAD] and the acquisition time [TACQ] and how these are described into Flowcode 5. Given my input hardware, the minimum TACQ is 1.25uS. I have thus set acquisition time to 6 program cycles. The crystal frequency is 12 MHz and is set to divide by 3. I am not sure if I have the correct understanding of Program Cycles and may have set this incorrectly. I have set the conversion speed to FOSC/4, this from the datasheet for a device clock of 4MHz.
I am also not sure what Clock Speed in Build>Project Options>General Options should be set to. Is it sufficient to set the clock in Configure Chip only or should it be done here as well?
Given the intermittent nature of the problem I have tried other settings without success. I have noticed that changing TACQ changes the data considerably but not the stability of the data.
Thanks Howard

[Enamul]

Hi,
If you are using FC V5 and your chip is in type 13 category in FC so that means this applies the same problem fix in the following post...
http://www.matrixmultimedia.com/mmforum ... 46&t=10980
Although in the post shows 18f4620 but this is true for following chips...

// ADC Type 13 Supported Devices ***********************************************************
// 18F2220, 18F2221, 18F2320, 18F2321, 18F24J10, 18F2410, 18F2420, 18F2423, 18F2450,
// 18F2455, 18F2480, 18F25J10, 18F2510, 18F2515, 18F2520, 18F2523, 18F2525, 18F2550,
// 18F2580, 18F2585, 18F2610, 18F2620, 18F2680, 18F4220, 18F4221, 18F4320, 18F4321,
// 18F44J10, 18F4410, 18F4420, 18F4423, 18F4450, 18F4455, 18F4480, 18F45J10, 18F4510,
// 18F4515, 18F4520, 18F4523, 18F4525, 18F4550, 18F4580, 18F4585, 18F4610, 18F4620,
// 18F4680, 18F4682, 18F4685
// *****************************************************************************************/

So the above discussion is true for your case if you are using Vref other than Vdd..in the "Edit Component Properties" window as i have shown in the attached picture.
About your question how FC deals following.. Mentioned setting causes..

Code: Select all

#define ADC_1_MX_ADC_ACTIME    6
#define ADC_1_MX_ADC_CONVSP    2

where

Code: Select all

adcon2 = Conv_Speed & 0x07;

this means for this setting

Code: Select all

adcon2=0x02

which means Tad = 0 and Fosc/32

I guess there is the problem..mapping of Fosc in FC is not matched with IC..

I have tried some other cases as well same findings..it doesn't match with ADCON2 requirement..

Enamul

[Benj]

Hello Enamul

I guess there is the problem..mapping of Fosc in FC is not matched with IC..

I have been through the FCDs today and updated the ADC component so that in v5.3 for PIC these ADC settings should again line up correctly on all the devices. I believe v5.3 for PIC will be available in the next week or so.

[Enamul]

Hi Ben,
It's nice to know that v5.3 is coming!

You are working excellent..Nice team
Enamul

[howard123]

Hi and thank you for the information. Sorry had only seen this now. regards Howard