This training solution provides a complete 40 hour course in the techniques of developing projects based on FPGAs using either Verilog or VHDL using an Altera FPGA and the free version of the Quartus design software, which requires registration with Altera.
The equipment is ideal for learning and for project work and students can go on to develop more advanced projects which might even include embedding NIOS processors. A full instructors' manual is available to download from the resources tab above.
Learning objectives/experiments include:
- FPGA design techniques
- Quartus development environment: top down and bottom up projects
- VHDL design language
- Verilog design language
- Combinational logic circuits: simple circuits, encoders, decoders, parity checkers, adders, subtractors, multipliers
- Sequential logic circuits: SR, D, JK flip flops, asynchronous up, down and BCD counters, synchronous binary up and down counters, state machines
- Project work