Error No. 2 pwm display avr atmega324p

[coffy]

hi,
AND FOR THE TIMER 0 (channel 1 and 2)TIMER 2(channel 6 and 7) phase correct pwm mode.
F(Hz) = fclk_I/O / (N * 510) with no adjustments PERIOD OVERFLOW (only 255), delete this setting
thank you
bruno

[Benj]

Hello Bruno,

Not sure what you are reporting as a bug there. Please could you provide more detail as to the problem you are experiencing.

[coffy]

channel6.png

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hi,
measured period T = 204μs and not T = 103μs
The frequency is fix for any value of PERIOD OVERFLOW
bruno

[Benj]

Hi Bruno,

It looks like the 324P has the period register for the 2 x Timer 1 PWM channels (Channel 3,4) but the 4 x Timer 0 and Timer 2 PWM channels are missing this functionality.

Not sure if we can easily make this distinction in the component but I will add a note in our to do list to have a look into this.

[coffy]

Hello,
One idea: configuration registers changed
bruno