PIC18F4550 - oscillator settings - CPU Sys CLK Select

[viki2000]

Hi,

Please have a look at the pictures below, where the PIC18F4550 oscillator settings are specified for:

http://i926.photobucket.com/albums/ad10 ... bc66c1.jpg
http://i926.photobucket.com/albums/ad10 ... 53175d.jpg
http://i926.photobucket.com/albums/ad10 ... c45492.jpg
http://i926.photobucket.com/albums/ad10 ... cd03a6.png
http://i926.photobucket.com/albums/ad10 ... 85c43a.jpg
http://i926.photobucket.com/albums/ad10 ... 0fdbf6.jpg

I have tested the settings for 20MHz crystal using PLL for USB and 24MHz for CPU clock to ensure compatibility with low speed USB speeds, therefore the parameters are:
A = 20MHz – the frequency of the external crystal/quartz
B = OSC Select = PLL Division PLLDIV2:PLLDIV0 = div by 5
C = Oscillator = HS+PLL = HSPLL = FOSC3:FOSC0 = C1
D = CPU Sys CLK Select = MCU Clock Division = CPU System Clock Postscaler = div by 3
Here is an “error”. It shows only OSC1/OSC2 dividing values: no divide which is divide by 1, then divide by 2 or 3 or 4. That is OK for OSC1/OSC2. If we choose PLL/2 it supposed to show as option to choose as divided by 2 or 3 or 4 or 6, but does not show the difference when we choose F = USB Clock Selection as 96MHz PLL/2. It remains as in case of OSC1/OSC2.
Important is that works, but it suppose to show different options for the division.
When I choose F = USB Clock Selection as 96MHz PLL/2 and D = CPU Sys CLK Select = div by 3, then it behaves as div by 4.
E = 24MHz = Clock speed (24000000 Hz)
F = USB Clock Selection as 96MHz PLL/2 = USBDIV bit

Any chance for correction in future updates of the FlowCode?

[Benj]

Hello,

I cannot do dynamic changes to the config text but I have re-worded the entries for the clock divisor.

Have a look and see if these are any better.

18F4550.fcdx

(29.13 KiB) Downloaded 343 times

The file needs to be placed here to function correctly: "C:\Program Files (x86)\Flowcode 6\FCD\PIC"

[viki2000]

Dear Benj,

Now looks fine.
Thank you for the corrections.